In area of telecommunications, signals are sent between devices for long distances over communication cables and/or fibers. These signals are not accompanied by a clock signal; hence, the device receiving the data signal must generate its own clock (known in the art as "clock recovery"). This clock is used to retime the incoming signal.
Typically, data is transmitted between devices as return-to-zero ("RZ") data. With RZ data, a logic "1" data pulse returns to zero prior to the end of a clock period, as shown in FIG. 1a. In the telecommunications industry, RZ data typically returns to zero halfway through a clock period. Additionally, for telecommunications, RZ data is typically transmitted in a bipolar form, shown in FIG. 1b, where a logic "1" may be of positive or negative polarity. Usually, the bipolar signal is split into positive and negative data, shown in FIGS. 1c and 1d, at the receiving portion of the system. Clock recovery can be performed before or after the positive and negative data is recombined. Clock recovery is typically performed prior to operations such as B3ZS decoding, bipolar violations, and similar operations, such that these operations can be performed synchronously.
A second data form is non-return-to-zero (NRZ) data. With NRZ data, a logic "1" data pulse does not return to zero at any time during the period, as shown in FIG. 1e. NRZ data types are most commonly found internal to the device. Because NRZ data is not suited for long distance transmission, it is rarely transmitted between devices, with the exception of a fiber-optic transmission system. In most cases, NRZ data contains all of its information in a single data stream; however, there may be cases in which NRZ data may be split into more than one data stream.
One prior art clock recovery circuit uses a resonant (ringing tank) clock circuit to generate a clock signal in response to received data. Ringing tank circuits present several problems. First, in order to maintain the circuit in a "ringing" condition, a minimum repetition rate of a data pulse is necessary. Further, ringing tank circuits are subject to temperature variations which may result in a drift in frequency. In order to maintain the circuits, a considerable amount of testing and adjusting is necessary to keep the ringing tank tuned to the appropriate frequency.
A second clock recovery circuit uses an analog phase-locked loop (PLL). These devices present the usual problems of imprecision of a analog circuit relative to digital techniques. Accordingly, a number of digital PLL circuits have been proposed for clock recovery. One of these is shown in U.S. Pat. No. 4,819,251 to Nelson. In this patent, a digital clock recovery circuit is presented which uses a delay line to produce a plurality of delayed sample signals, which are then used to sample incoming data in a phase detector. The resultant sample data is then resampled by the tentatively correct apparatus clock output signal. The resampled data provides a direct indication of the phase difference between the data and the clock and the value can be obtained using a summing circuit. If the summed amount is outside an allowable range of values, a phase altering signal is applied to an oscillator to change the phase of the apparatus clock output signal. While circuits such as these overcome some of the problems associated with analog clock recovery circuits, such as precision tuning of the VCO or VCXO, phase adjustments, high cost and the need to use precision analog parts, these digital clock recovery circuits are not suited to clock recovery from RZ data and/or require high frequency clock sources in order to operate.
In some situations, it is highly desirable to recover a clock from signals of two different frequencies. DS3 and STS-1 signals, for example, are almost identical in their transmitted characteristics, each being RZ bipolar signals which return to zero halfway through the period. The DS3 has a nominal frequency of 44.736 MHz, while the STS-1 has a nominal frequency of 51.84 MHz. Since both of these signals occupy equivalent levels in the telecommunications hierarchy, it will be common for a particular piece of equipment to accommodate both types of data. Consequently, a clock recovery circuit which can recover a clock from both types of signals would be a great benefit to avoid duplicate circuitry for each type of signal. Heretofore, prior art clock recovery devices do not easily switch between signals of different frequencies.
Therefore a need has arisen in the industry for an accurate clock recovery system, which is capable of handling multiple frequency input signals, has a large retime margin, and is capable of handling both RZ and NRZ data inputs.